As technology has progressed, the size of integrated circuit devices has minimized to very deep sub-micron technology and further towards sub-0.1 micron technology, consequently reducing the operating voltage of the device core. However, I/O circuits keep operating at higher voltages than the core as they must interface with other devices operating at higher voltage.
MOS devices compatible with higher voltages are required to be driven by lower voltages, which is increasingly difficult as the technology of the core moves towards lower dimension regimes.
To achieve core voltage to I/O translation, conventional translators uses latch type circuit. FIG. 1 illustrates a prior art low to high voltage translator circuit as taught in U.S. Pat. No. 5,422,523. The input to the translator IN 2 is a signal having a low voltage swing. Inverter 10 inverts the input signal 2. These signals drive the gate of N-channel devices 8 and 12. Since transistors 8 and 12 are devices that are compatible with higher voltages, the threshold voltage of these devices is, therefore, high. When the gate of these transistors is driven by signals having a lower voltage swing, the device is very slow, needing a large area to drive the output at the desired slew rate. As the lower voltage level decreases with the feature size, at a particular, lower voltage input signal 2, transistors 8 and 12 may cease to operate altogether. Another problem with the circuit shown in FIG. 1 is that whenever the OUT signal at node 14 is rising, there is a glitch due to bootstrapping. This glitch is likely to increase as larger and larger sized N-channel transistors are used.
What is desired, therefore, is a circuit that can accept a low voltage swing and translate it to a high level while controlling the delay between signal transitions to avoid glitches.